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Digital Logic covers number systems, Boolean algebra, combinational and sequential circuits, Karnaugh maps, flip-flops, and finite state machines. Exams are procedural — minimize this function, design this counter, trace this timing diagram — so accuracy under time pressure is everything. Practice exams with full solutions let you verify every K-map grouping and state transition.

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Topics typically tested

  • Number systems & binary arithmetic
  • Boolean algebra & logic gates
  • Karnaugh map minimization
  • Combinational circuit design (mux, decoder, adder)
  • Latches, flip-flops & registers
  • Finite state machine design

Sample Digital Logic Design exam questions

Three original questions in the style of a real Digital Logic Design exam, each with a worked solution. Your own practice exam can be built from your course's notes and syllabus.

Question 1Multiple choiceKarnaugh map minimization

A four-variable Boolean function is specified by its minterms: F(A,B,C,D)=∑m(0,2,5,7,8,10,13,15)F(A,B,C,D) = \sum m(0, 2, 5, 7, 8, 10, 13, 15), where AA is the most significant bit of each minterm index. Using a Karnaugh map, which expression is the minimal sum-of-products form of FF?

  1. A.

    B‾ D‾+BD\overline{B}\,\overline{D} + BD

  2. B.

    A‾ B‾ D‾+AB‾ D‾+BD\overline{A}\,\overline{B}\,\overline{D} + A\overline{B}\,\overline{D} + BD

  3. C.

    B‾ D‾+A‾BD+ABD\overline{B}\,\overline{D} + \overline{A}BD + ABD

  4. D.

    B‾D+BD‾\overline{B}D + B\overline{D}

Worked solution
Answer:A

Draw the map with rows AB=00,01,11,10AB = 00, 01, 11, 10 and columns CD=00,01,11,10CD = 00, 01, 11, 10 (Gray-code order, so neighbouring cells differ in exactly one variable), and place a 1 in each listed minterm.

Minterms 0, 2, 8 and 10 occupy the four corner cells (rows AB=00AB = 00 and 1010, columns CD=00CD = 00 and 1010). Because the map wraps around both edges, the corners form a single group of four. Across that group AA and CC both change while B=0B = 0 and D=0D = 0 stay fixed, so the implicant is B‾ D‾\overline{B}\,\overline{D}.

Minterms 5, 7, 13 and 15 fill the centre 2×22\times 2 block (rows AB=01,11AB = 01, 11, columns CD=01,11CD = 01, 11). Here AA and CC change while B=1B = 1 and D=1D = 1, giving BDBD.

Each group contains a 1 that no other prime implicant covers, so both are essential, and together they cover all eight minterms:

F=B‾ D‾+BD,F = \overline{B}\,\overline{D} + BD,

which is simply BB XNOR DD. Spot check: minterm 10 is AB‾CD‾A\overline{B}C\overline{D}, where B‾ D‾=1\overline{B}\,\overline{D} = 1, so F=1F = 1 as required; minterm 6 is A‾BCD‾\overline{A}BC\overline{D}, where both terms are 0, so F=0F = 0, and 6 is indeed absent from the list.

Option B is the common slip: treating the corners as two separate pairs instead of one wrapped group of four leaves AA in both terms. Option C fails to merge the two vertical pairs of the centre block. Option D is the complement of the answer (BB XOR DD): it is what you get by grouping the eight 0-cells (minterms 1, 3, 4, 6, 9, 11, 12, 14) instead of the 1-cells.

F=B‾ D‾+BDF = \overline{B}\,\overline{D} + BD (option A).

Question 2Short answerNumber systems & binary arithmetic

An 8-bit processor stores signed integers in two's-complement form. It adds the two 8-bit values 0x6C and 0x45. Give the 8-bit result in hexadecimal, give its value as a signed decimal integer, and state whether the overflow flag (V) and the carry flag (C) are set after the addition.

Worked solution
Answer:

0xB1; −79 as a signed value; V = 1 (overflow), C = 0

Convert both operands to binary: 0x6C = 0110 1100 (decimal 108) and 0x45 = 0100 0101 (decimal 69). Add column by column from the right:

  0110 1100
+ 0100 0101
-----------
  1011 0001

The sum is 1011 0001 = 0xB1. There is no carry out of bit 7, so the carry flag is C = 0.

Interpreting 1011 0001 as two's complement: the sign bit is 1, so the value is negative. Its magnitude is found by inverting and adding 1: 0100 1110 + 1 = 0100 1111 = 79, so the result is −79.

Decimal check: 108 + 69 = 177. The largest 8-bit signed value is +127, so 177 does not fit; wrapping around by 256 gives 177 − 256 = −79, which confirms the signed reading.

Overflow is the key observation: two positive operands produced a negative result, which can only happen when the true sum is outside the representable range. Equivalently, the carry into the sign bit (1) differs from the carry out of it (0). Therefore V = 1. Note that C and V are independent: C describes unsigned arithmetic, and 177 fits in an unsigned byte, so C = 0 is correct even though V = 1.

Result 0xB1, signed value −79, V = 1, C = 0.

Question 3Worked problemFinite state machine design

Design a synchronous Moore machine with a single input xx and a single output zz that detects the bit pattern 110 on xx: the machine enters an output state (where z=1z = 1) in the clock cycle immediately after the third bit of a 110 pattern has arrived, and it keeps scanning afterwards (the stream 1, 1, 0, 1, 1, 0 asserts zz twice). Use four states S0 (no useful prefix), S1 (last bit was 1), S2 (last two bits were 11) and S3 (110 just completed, z=1z = 1), implemented with two D flip-flops Q1Q0Q_1Q_0 encoded S0 = 00, S1 = 01, S2 = 10, S3 = 11. (a) Give the state-transition table. (b) Derive minimal sum-of-products expressions for D1D_1, D0D_0 and zz in terms of Q1Q_1, Q0Q_0 and xx.

Worked solution
Answer:

D1=Q1‾Q0x+Q1Q0‾D_1 = \overline{Q_1}Q_0x + Q_1\overline{Q_0}; D0=Q1‾ Q0‾ x+Q1Q0‾ x‾+Q1Q0xD_0 = \overline{Q_1}\,\overline{Q_0}\,x + Q_1\overline{Q_0}\,\overline{x} + Q_1Q_0x; z=Q1Q0z = Q_1Q_0

(a) Decide where each state goes on each input. From S0, a 0 is useless (stay in S0) and a 1 starts a prefix (go to S1). From S1, a 0 breaks the pattern, since 10 is not a prefix of 110 (go to S0), and a 1 gives 11 (go to S2). From S2, a 0 completes 110 (go to S3) and a 1 leaves the last two bits as 11 (stay in S2). From S3, a 0 gives S0, and a 1 is the start of a new pattern (go to S1). With the given encoding, the next-state values D1D0D_1D_0 and the output are:

Q1Q0Q_1Q_0xxD1D0D_1D_0zz
000000
001010
010000
011100
100110
101100
110001
111011

(b) D1=1D_1 = 1 in the rows Q1Q0x=011,100,101Q_1Q_0x = 011, 100, 101. The last two differ only in xx and merge into Q1Q0‾Q_1\overline{Q_0}; 011 has no neighbour, so

D1=Q1‾Q0x+Q1Q0‾.D_1 = \overline{Q_1}Q_0x + Q_1\overline{Q_0}.

D0=1D_0 = 1 in the rows 001, 100 and 111. No two of these differ in exactly one bit, so nothing merges:

D0=Q1‾ Q0‾ x+Q1Q0‾ x‾+Q1Q0x.D_0 = \overline{Q_1}\,\overline{Q_0}\,x + Q_1\overline{Q_0}\,\overline{x} + Q_1Q_0x.

The output of a Moore machine depends only on the state, and only S3 outputs 1, so z=Q1Q0z = Q_1Q_0.

Check by running the stream 1, 1, 0, 1 through the equations: from 00, x=1x = 1 gives 01; x=1x = 1 gives 10; x=0x = 0 gives 11, so z=1z = 1 in the cycle after the 0 arrives; then x=1x = 1 gives 01, correctly treating that 1 as the start of a new pattern.

D1=Q1‾Q0x+Q1Q0‾D_1 = \overline{Q_1}Q_0x + Q_1\overline{Q_0}, D0=Q1‾ Q0‾ x+Q1Q0‾ x‾+Q1Q0xD_0 = \overline{Q_1}\,\overline{Q_0}\,x + Q_1\overline{Q_0}\,\overline{x} + Q_1Q_0x, z=Q1Q0z = Q_1Q_0.

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