BJT DC Bias Analysis

Finding quiescent operating point (I_C, V_CE) of a BJT amplifier

Golden Rule: Assume active region (V_BE = 0.7 V, I_C = βI_B). Apply KVL around the base and collector loops to find I_B and V_CE, then verify that V_CE > V_CE(sat) ≈ 0.2 V.

• Step 1: Identify the bias topology — For voltage divider bias (most common): R1 and R2 form a Thevenin equivalent for the base. Identify R1, R2, RC, RE, VCC. For fixed bias: only RB and RC present.
• Step 2: Find Thevenin base voltage and resistance — Vth = VCC × R2 / (R1 + R2). Rth = R1 ∥ R2. This converts the voltage divider into a single Thevenin source driving the base through Rth.
• Step 3: Apply KVL around the base loop — Since I_E = (β + 1)I_B: Vth = I_B·Rth + 0.7 + (β+1)I_B·RE. Solve for I_B. Then I_C = β·I_B and I_E = (β+1)·I_B.
• Step 4: Apply KVL around the collector loop — VCC = I_C·RC + V_CE + I_E·RE. Solve for V_CE. Since I_E ≈ I_C for large β, V_CE ≈ VCC − I_C(RC + RE).
• Step 5: Verify active region — Active region requires V_CE > 0.2 V. If V_CE < 0.2 V, the transistor is saturated and you must re-solve with V_CE = V_CE(sat) = 0.2 V. Also verify V_BE = 0.7 V is consistent.